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Link带参数的Verilog模块(Design Compiler)

2018-04-22 来源:博客园/Kathyra

在Design Compiler中,Verilog文件可以用read_verilog命令读入,用link命令连接。以下是连接两个文件RegisterFile.v和Test.v的脚本:

# Read design files
file mkdir ./work
define_design_lib WORK -path ./work
read_verilog {RegisterFile.v Test.v}
current_design Test
link

其中define_design_lib指定中间文件存放到work目录,否则默认会存放到当前目录,文件多了看起来比较混乱。另外,建议使用current_design命令显式指定当前模块。

如果没有使用参数(Parameter),这个脚本工作的很好,但是一旦在例化模块时指定了参数值,则会出错:

Information: Building the design 'RegisterFile' instantiated from design 'Test' with
	the parameters "2,1". (HDL-193)
Warning: Cannot find the design 'RegisterFile' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'RegisterFile' in 'Test'. (LINK-5)
0

查看前面的信息也会发现,实际上模块是使用默认参数例化的,所以连接时找不到被例化模块的实现:

Inferred memory devices in process
	in routine RegisterFile line 21 in file
		'./rtl/RegisterFile.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    RegArray_reg     | Flip-flop | 1024  |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
 
Inferred memory devices in process
	in routine RegisterFile line 33 in file
		'./rtl/RegisterFile.v'.
=================================================================================
|     Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
=================================================================================
| LatchedReadAddr_1_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| LatchedReadAddr_2_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
=================================================================================

那么,使用了带参数的模块,就要使用analyze和elaborate命令连接,脚本如下:

# Read design files
file mkdir ./work
define_design_lib WORK -path ./work
analyze -format verilog {RegisterFile.v Test.v}
elaborate Test

现在查看输出信息,就会发现确实是按照例化时指定的参数编译模块的,并且连接成功了:

Inferred memory devices in process
	in routine RegisterFile_W_DATA2_W_ADDR1 line 21 in file
		'./rtl/RegisterFile.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    RegArray_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
 
Inferred memory devices in process
	in routine RegisterFile_W_DATA2_W_ADDR1 line 33 in file
		'./rtl/RegisterFile.v'.
=================================================================================
|     Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
=================================================================================
| LatchedReadAddr_1_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| LatchedReadAddr_2_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
=================================================================================
Presto compilation completed successfully.
1

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